The parasitic injection of charge onto an output terminal, for example, of a hold capacitor in a sample and hold circuit, can be problematic. Parasitic charge occurs when a complementary metal-oxide semiconductor (CMOS) transistor is switched off.
CMOS transistors comprise a source, a gate and a drain connections. The source and drain are formed using the same type of doping, either n or p. Generally, the gate is doped with a dopant opposite from the drain and the source. The doped region beneath the gate separates the drain from the source, and prevents current from flowing between the source and the drain. When voltage is applied to the gate, a channel is formed in the doped region beneath the gate, and current passes between the source and the drain through the channel i.e., the transistor is ON. When voltage is removed from the gate, the transistor is OFF However, the channel does not close instantly. As the transistor is turning OFF, a channel charge flows through the channel to the source or the drain. The amount of channel charge is a non-linear function of the voltage applied at the source of the transistor. This is called charge injection, and results in the problematic parasitic charge at the output terminal.
It is beneficial to prevent the parasitic charge from affecting the output on the output terminal of a device. Presently, compensation techniques for parasitic charge use capacitors or use a half-switch discharge circuit. Compensation capacitors only move the charge injection curve so that it is at its minimum at the midpoint of the signal range, and the charge injection is symmetrical about this point. Compensation capacitors do not affect the absolute value of the charge injected at the extremes of the signal range; they simply offset the charge injection curve. Using compensation capacitor also obviously adds capacitance, which affects bandwidth, overall circuit impedance and the like. The half switch discharge circuit is effective but it is costly in terms of die area. For low on-resistance switches, it is not an option as the size of the half switch is excessive and prohibitive. There is also a capacitive penalty with this solution.